Wafer-Level Test Infrastructure for Higher Parallel Wafer Level Testing of SoC

Written By Jae Park

“Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip” was published by researchers at Inha University and Teradyne.

Jae Park
Previous

SiC MOSFETs, Global Battery Market, Power Solutions For Data Centers: Power Electronics Week Insights
Next

RISC-V High Performance Multicore and GPU SoC Platform For Safety Critical System