Nearly Invisible: Defect Detection Below 5nm

Detecting sub-5nm defects creates huge challenges for chipmakers, challenges that have a direct impact on yield, reliability, and profitability.

In addition to being smaller and harder to detect, defects are often hidden beneath intricate device structures and packaging schemes. Moreover, traditional optical and electrical probing methods, trusted for decades, are proving inadequate against the complexity of modern chip architectures.

“The number of high precision parametric measurements we can pull out of a single advanced AI processor is immense — tens of thousands of data points from just one package,” says Jack Lewis, CTO at Modus Test. “Multiply that across multiple packages, across test vehicle lots, and now you have millions of samples across every die layer and interconnect. That’s the kind of density you need to find those elusive, one-in-a-million defects and provide the design and defect detection feedback early in the process development, long before they show up during production ramps.”